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HD74LVC74
Dual D-type Flip Flops with Preset and Clear
REJ03D0347-0400Z (Previous ADE-205-066C (Z)) Rev.4.00 Jul. 22, 2004
Description
The HD74LVC74 has independent data, preset, clear, and clock inputs Q and Q outputs in a 14 pin package. The logic level present at the data input is transferred to the output during the positive going transition of the clock pulse. Preset and clear are independent of the clock and accomplished by a low level at the appropriate input. Low voltage and highspeed operation is suitable at the battery drive product (note type personal computer) and low power consumption extends the life of a battery for long time operation.
Features
* * * * * * VCC = 2.0 V to 5.5 V All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25C) High output current 24 mA (@VCC = 3.0 V to 5.5 V) Ordering Information
Package Type SOP-14 pin (JEITA) TSSOP-14 pin Package Code FP-14DAV TTP-14DV Package Abbreviation FP T Taping Abbreviation (Quantity) EL (2,000 pcs/reel) ELL (2,000 pcs/reel)
Part Name HD74LVC74FPEL HD74LVC74TELL
Note: Please consult the sales office for the above package availability.
Function Table
Inputs PR L H L H H H H H H: L: X: : : Q0 : Note: CLR H L L H H H H H CK X X X L H D X X X H L X X X Outputs Q H L H *1 H L Q0 Q0 Q0 Q L H H *1 L H Q0 Q0 Q0
High level Low level Immaterial High to Low transition Low to high transition Level to Q before the indicated steady input conditions was established. 1. Q and Q will remain high as long as preset and clear are low, but Q and Q are unpredictable, if preset and clear go high simultaneously.
Rev.4.00 Jul. 22, 2004 page 1 of 6
HD74LVC74
Pin Arrangement
1CLR
1
CK D PR CLR
14 VCC 13
2CLR
1D 2 1CK 3
Q
Q
12 2D 11 2CK
1PR 4 1Q 5 1Q 6 GND 7
D CK
10 2PR 9 2Q 8 2Q
CLR PR Q Q
(Top view)
Absolute Maximum Ratings
Item Supply voltage Input diode current Input voltage Output diode current Output voltage Output current VCC, GND current / pin Storage temperature Symbol VCC IIK VI IOK VO IO ICC or IGND Tstg Ratings -0.5 to 6.0 -50 -0.5 to 6.0 -50 50 -0.5 to VCC +0.5 50 100 -65 to +150 Unit V mA V mA V mA mA C Conditions VI = -0.5 V VO = -0.5 V VO = VCC +0.5 V
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time.
Recommended Operating Conditions
Item Supply voltage Input / output voltage Operating temperature Output current Symbol VCC VI VO Ta IOH IOL Input rise / fall time *1 tr, tf Ratings 1.5 to 5.5 2.0 to 5.5 0 to 5.5 0 to VCC -40 to 85 -12 -24 *2 12 24 *2 10 Unit V V C mA mA ns/V Conditions Data retention At operation PR, CLR, CK, D Q, Q VCC = 2.7 V VCC = 3.0 V to 5.5 V VCC = 2.7 V VCC = 3.0 V to 5.5 V
Notes: 1. This item guarantees maximum limit when one input switches.
Waveform: Refer to test circuit of switching characteristics.
2. Duty cycle 50%
Rev.4.00 Jul. 22, 2004 page 2 of 6
HD74LVC74
Electrical Characteristics
Ta = -40 to 85C Item Input voltage Symbol VIH VIL Output voltage VOH VCC (V) 2.7 to 3.6 4.5 to 5.5 2.7 to 3.6 4.5 to 5.5 2.7 to 5.5 2.7 3.0 3.0 4.5 2.7 to 5.5 2.7 3.0 4.5 0 to 5.5 5.5 3.0 to 3.6 Min 2.0 VCCx0.7 -- -- VCC -0.2 2.2 2.4 2.0 3.8 -- -- -- -- -- -- -- Max -- -- 0.8 VCCx0.3 -- -- -- -- -- 0.2 0.4 0.55 0.55 5.0 20 500 Unit V V V IOH = -100 A IOH = -12 mA IOH = -24 mA V IOL = 100 A IOL = 12 mA IOL = 24 mA VIN = 5.5 V or GND VIN = VCC or GND VIN = one input at (VCC -0.6)V, other inputs at VCC or GND Test Conditions
VOL
Input current Quiescent supply current
IIN ICC ICC
A A A
Rev.4.00 Jul. 22, 2004 page 3 of 6
HD74LVC74
Switching Characteristics
Ta = -40 to 85C Item Maximum clock frequency Symbol fmax VCC (V) 2.7 3.30.3 5.00.5 2.7 3.30.3 5.00.5 2.7 3.30.3 5.00.5 2.7 3.30.3 5.00.5 2.7 3.30.3 5.00.5 2.7 3.30.3 5.00.5 2.7 3.30.3 5.00.5 2.7 3.30.3 5.00.5 2.7 2.7 Min 150.0 150.0 150.0 -- 1.5 -- -- 1.5 -- 4.0 3.0 3.0 2.0 2.0 2.0 4.0 4.0 4.0 6.0 5.0 4.0 3.0 2.0 2.0 -- -- Typ -- -- -- 6.0 5.0 4.0 6.5 5.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 3.0 15.0 Max -- -- -- 9.0 8.0 6.5 9.0 8.0 6.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit MHz From (Input) To (Output)
Propagation delay time
tPLH tPHL tPLH tPHL
ns
CLK
Q, Q
ns
PR or CLR Q, Q
Setup time
tsu
ns
Hold time
th
ns
Pulse width
tw
ns
CK
PR or CLR
Recovery time
trec
ns
Input capacitance Output capacitance
CIN CO
pF pF
Test Circuit
Input VCC
Zout = 50 Input
See Function Table
Pulse Generator
PR D
Q CL = 50 pF 450 50 Scope
Output Q
Pulse Generator Zout = 50
CK CLR
Q CL = 50 pF 450 50 Scope
Output Q
Notes:
1. CL includes probe and jig capacitance. 2. Test is put into the each flip flops.
Rev.4.00 Jul. 22, 2004 page 4 of 6
HD74LVC74 Waveforms
tf Input CLR 90 % Vref 10 % tw tf 90 % Input PR t rec tr Input CK 90 % Vref 10 % tf 90 % Vref 10 % t w (H) Vref t w (L) Vref Vref Vref tr 90 % Vref 10 % 10 % tw t rec VIH Vref GND t h (H) t s (L) t h (L) VIH Vref Vref GND t PHL Vref t PLH VOH Output Q Vref Vref Vref VOL t PLH Output Q Vref t PHL Vref t PLH Vref t PHL VOH Vref VOL Symbol VIH Vref VCC = 2.7 V, 3.30.3 V VCC = 5.00.5 V 2.7 V VCC 1.5 V 50%VCC VIH GND tr 90 % Vref 10 % VIH GND
t s (H) Input D 90 % Vref 10 % tr t PHL
90 % Vref 10 % tf t PLH
Notes:
1. tr = 2.5 ns, tf = 2.5 ns 2. Clock pulse input waveform : PRR = 10 MHz, duty cycle 50% 3. Data input waveform : PRR = 5 MHz, duty cycle 50%
Rev.4.00 Jul. 22, 2004 page 5 of 6
HD74LVC74
Package Dimensions
As of January, 2003
Unit: mm
10.06 10.5 Max 14 8
1
7
5.5
*0.20 0.05
2.20 Max
0.20 7.80 + 0.30 -
1.42 Max
1.15 0 - 8 0.70 0.20
1.27 *0.40 0.06
0.12 M
Package Code JEDEC JEITA Mass (reference value) FP-14DAV -- Conforms 0.23 g
*Ni/Pd/Au plating
0.10 0.10
0.15
As of January, 2003
Unit: mm
5.00 5.30 Max 14 8
1
7 0.65 1.0 0.13 M 6.40 0.20 0.83 Max 0 - 8 0.50 0.10
*0.20 0.05
4.40
*0.15 0.05
1.10 Max
0.10
0.07 +0.03 -0.04
*Ni/Pd/Au plating
Package Code JEDEC JEITA Mass (reference value)
TTP-14DV -- -- 0.05 g
Rev.4.00 Jul. 22, 2004 page 6 of 6
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